1. Field of the Invention
The present invention relates to a compound semiconductor device, more specifically to an electrode structure capable of preventing deterioration of a semiconductor caused by a particular type of metal reacting there with, and enhancing the strength of mounting a metal electrode on a certain section so as to prevent the metal electrode from falling off, thereby increasing the reliability of the device, and simplifying the manufacturing process.
2. Description of the Related Art
Generally, an electronic device such as a transistor or a diode, in which a compound semiconductor is used, or a compound semiconductor device such as an optical device including a laser diode or photodiode, has a metal electrode designed for the connection with an external electric circuit. Conventionally, the connection between a metal electrode and an external electric circuit is carried out in the following manner. That is, with regard to one of the electrodes, a compound semiconductor chip is mounted on a wiring pattern of a substrate, whereas with regard to the other electrode, a wire of Au, Al or the like is bonded. In this connecting method, a wire must be bonded, and therefore the manufacturing process becomes complex. The addition of the wire causes an increase in the electric capacity or inductance. Therefore, with the conventional method, it is difficult to obtain the electrical performances which the compound semiconductor originally possesses.
As a solution to this problem, recently, a so-called flip-chip type structure, capable of achieving the electrical connection by simply mounting a compound semiconductor device. The following is a description of the compound semiconductor device, taking an example of the electrode structure in a semiconductor light-receiving element for optical communications.
FIG. 1 is a cross section showing a conventional semiconductor light-receiving element of a flip-chip type, in which light is made incident from the rear surface. The light-receiving element 6 consists of an N.sup.+ -InP substrate 1, an N-InP buffer layer 2, an InGaAs light absorption layer 3 and an N.sup.- -InP cap layer 4.
More specifically, first, the N-InP buffer layer 2 is provided on the N.sup.+ -InP substrate 1, and the InGaAs light absorption layer 3 is provided on the N-InP buffer layer 2. Then, the N.sup.- -InP cap layer 4 is formed on the InGaAs light absorption layer 3.
After that, for example, Zn is implanted selectively into the cap layer 4 as a P-type impurity, and a P-type impurity region 5 is formed in the light absorption layer 3 and the cap layer 4. Thus, a PN junction is formed between the P-type impurity region 5 and the light absorbing layer 3. Next, the cap layer 4, the light receiving layer 3 and the buffer layer 2 are etched, and these layers 4, 3 and 2 are separated into a region 7 in which a P-type electrode is formed (P-type electrode formation region) and a region 8 in which an N-type electrode is formed (N-type electrode formation region).
An insulating film 9 is provided on the cap layer 4 in the P-type electrode formation region 7. After that, a contact hole 9a is formed in the insulating film 9 at a location above the P-type impurity region 5. Next, a first electrode pad 13, which consists of a Ti layer 10, a Pt layer 11 and an Au layer 12, is provided in the contact hole 9a and on the insulating film 9, and a second electrode pad 14, which consists of the Ti layer 10, the Pt layer 11 and the Au layer 12, is provided on the cap layer 4 of the N-type electrode formation region 8.
After that, solder bumps (not shown) are formed on the first and second electrode pads 13 and 14. Next, a lens 15 is formed on the rear surface side of the N.sup.+ -InP substrate 1, on which light is made incident. A reflection preventing film 16 is formed on the lens 15.
FIG. 2 is a cross section showing an enlarged view of the main portion of the peripheral portion of the electrode obtained when the semiconductor light-receiving element shown in FIG. 1 is mounted on a mounting member. The flip-chip type semiconductor light receiving element, to which light is applied from the rear surface, is mounted on the mounting member 18 on which an electrode pattern 19 which corresponds to each of the electrode pads 13 and 14 is formed in advance with solder bumps 17 by the thermal pressure adhesion method.
The semiconductor light receiving element does not require a wire for wiring, and therefore the manufacture process can be simplified, and decreases in electric capacity and inductance can be suppressed. For the above-described reason, the above-described light receiving element has become the main focus of studies relating to the field of large capacity light receiving system, the demand of which has recently increased in recent times.
In the conventional rear-surface light incident flip-chip type semiconductor light receiving element, a possible pattern for the electrode pattern 19 is restricted, and therefore the area of the joint of the Ti layer 10, and the electrode forming regions 7 and 8 is rendered small as compared to the area of the chip surface. As a result, a stress is concentrated on the joint of the Ti layer 10, and the electrode forming regions 7 and 8 after the semiconductor light-receiving element is mounted on the mounting member 18, and therefore the semiconductor light receiving element, in some cases, fall off from the joint. In short, in the conventional semiconductor light-receiving element, a sufficient junction strength, which is required for preventing the falling-off of the device, cannot be obtained. As a solution to this problem, it may be considered that the area of the junction should be increased; however when the area of the junction is increased, the area of the PN junction is inevitably increased. With this increment, the electric capacity in the PN junction is increased, resulting in degradation of the performances of the semiconductor light receiving element.
Further, as shown in FIG. 2, the solder bumps 17 are melted on the electrode pad 13 and flows on the side surface of the electrode pad 13 in the mounting step. Consequently, a component such as Au or Sn, contained in the solder bumps 17 which have remained on the side surface, is not blocked by the Pt layer 11, which was supposed to serve as a barrier layer and prevent such entering of the solder components. Therefore, as shown in FIG. 3, the component flows onto the Ti layer 10, which is a contact layer, or underneath the layer. As a result, the component such as Au or Sn is diffused in the cap layer 4, which is a compound semiconductor region, and a region 20, which is made as the solder component erodes the cap layer 4, is formed. Due to the diffusion of Au or Sn, the PN junction of the semiconductor is destroyed, and the electrical or optical characteristics of the semiconductor element are degraded. The destruction of the junction may occur in the process of the mounting step; however it gradually proceeds when the compound semiconductor device obtained after the mounting process is used in practice. This results in a low long-term reliability of the device, which is particularly a serious problem in the case of the large-capacity optical communication system, for example.
In order to solve such a problem, the following idea has been proposed. That is, for example, the distance L from the contact hole 9a to the end of the first electrode pad 13 shown in FIG. 3 is increased so as to make the component Au or Sn not easily entering into the contact hole 9a. As the first technique, it is a possibility that the distance L is increased by expanding the first electrode pad 13 by the periphery thereof. With this expansion, the periphery of the P-type impurity region 5 expands outwards along the periphery of the first electrode pad 13. Consequently, the area of the PN junction of the P-type impurity region 5 increases to a certain degree; however it cannot be increased to a sufficient level due to the restrictions of electrical capacity. Therefore, the first technique is not very appropriate. As the second method, it is a possibility that the distance L is increased by reducing the size of the contact hole 9a of the insulating film 9. In this case, the contact area between the first electrode pad 13 and the electrode forming region 7 is made small; however it is not desired to reduce the size of the contact area very much because of the restriction of the contact resistance. In practice, it is difficult to increase the distance L to a sufficient level. Thus, with the conventional technique, the problem of a low long-term reliability cannot be solved.